Hot-Carrier Reliability of MOS VLSI Circuits

As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.

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1. Introduction.- 1.1. The Concept of IC Reliability.- 1.2. Design-for-Reliability.- 1.3. VLSI Reliability Problems.- 1.4. Gradual Degradation versus Catastrophic Failures.- 1.5. Hot-Carrier Effects.- 1.6. Overview of the Book.- References.- 2. Oxide Degradation Mechanisms in Mos Transistors.- 2.1. Introduction.- 2.2. MOS Transistor: A Qualitative View.- 2.3. The Nature of Gate Oxide Damage in MOSFETs.- 2.4. Injection of Hot Carriers into Gate Oxide.- 2.5. Oxide Traps and Charge Trapping.- 2.6. Interface Trap Generation.- 2.7. Bias Dependence of Degradation Mechanisms.- 2.8. Degradation under Dynamic Operating Conditions.- 2.9. Effects of Hot-Carrier Damage on Device Characteristics.- 2.10. Hot-Carrier Induced Degradation of pMOS Transistors.- References.- 3.Modeling of Degradation Mechanisms.- 3.1. Preliminary Remarks.- 3.2. Quasi-Elastic Scattering Current Model.- 3.3. Charge (Electron) Trapping Model.- 3.4. Impact Ionization Current Model.- 3.5. Interface Trap Generation Model.- 3.6. Trap Generation under Dynamic Operating Conditions.- References.- 4. Modeling of Damaged Mosfets.- 4.1. Introduction.- 4.2. Representation of Hot-Carrier Induced Oxide Damage.- 4.3. Two-Dimensional Modeling of Damaged MOSFETs.- 4.4. Empirical One-Dimensional Modeling.- 4.5. An Analytical Damaged MOSFET Model.- 4.6. Consideration of Channel Velocity Limitations.- 4.7. Pseudo Two-Dimensional Modeling of Damaged MOSFETs.- 4.8. Table-Based Modeling Approaches.- References.- 5. Transistor-Level Simulation for Circuit Reliability.- 5.1. Introduction.- 5.2. Review of Circuit Reliability Simulation Tools.- 5.3. Circuit Reliability Simulation Using iSMILE: A Case Study.- 5.4. Circuit Simulation Examples.- 5.5. Evaluation of the Simulation Algorithm.- 5.6. Identification of Critical Devices.- References.- 6. Fast Timing Simulation for Circuit Reliability.- 6.1. Introduction.- 6.2. ILLIADS-R: A Fast Timing and Reliability Simulator.- 6.3. Fast Dynamic Reliability Simulation.- 6.4. Circuit Simulation Examples with ILLIADS-R.- 6.5. iDSIM2: Hierarchical Circuit Reliability Simulation.- References.- 7. Macromodeling of Hot-Carrier Induced Degradation in Mos Circuits.- 7.1. Introduction.- 7.2. Macromodel Development: Starting Assumptions.- 7.3. Degradation Macromodel for CMOS Inverters.- 7.4. Degradation Macromodel for nMOS Pass Gates.- 7.5. Application of the Macromodel to Inverter Chain Circuits.- 7.6. Application of the Macromodel to CMOS Logic Circuits.- References.- 8. Circuit Design for Reliability.- 8.1. Introduction.- 8.2. Device-Level Measures.- 8.3. Circuit-Level Measures.- 8.4. Rule-Based Diagnosis of Circuit Reliability.- References.