Integrated Circuit Manufacturability

About the Editors... Jose Pineda de Gyvez is an associate professor in the Department of Electrical Engineering, holding a joint faculty appointment with the Department of Computer Science, at Texas A&M University. Dr. Pineda de Gyvez was associate editor of technology for IEEE Transactions on Semiconductor Manufacturing and associate editor for cellular neural networks for IEEE Transactions on Circuits and Systems: Part 1. Dhiraj K. Pradhan is currently a visiting professor with the Department of Electrical Engineering at Stanford University (on leave from Texas A&M University.) Prior to joining Texas A&M, he served as professor and coordinator of computer engineering at the University of Massachusetts. Dr. Pradhan has contributed to VLSI CAD and test fault-tolerant computing, computer architecture, and parallel processing research with major publications in journals and conferences over the last 25 years.

Electrical Engineering Integrated Circuit Manufacturability The Art of Process and Design Integration Integrated Circuit Manufacturability provides comprehensive coverage of the process and design variables that determine the ease and feasibility of the fabrication (or manufacturability) of contemporary VLSI systems and circuits. This book progresses from semiconductor processing to electrical design to system architecture. The material provides a theoretical background as well as case studies, examining the entire design for the manufacturing path from circuit to silicon. Each chapter includes tutorial and practical applications coverage. Integrated Circuit Manufacturability illustrates the implications of manufacturability at every level of abstraction, including the effects of defects on the layout, their mapping to electrical faults, and the corresponding approaches to detect such faults. The reader will be introduced to key practical issues normally applied in industry and usually required by quality, product, and design engineering departments in today's design practices:

Defect Monitoring and Characterization; Digital CMOS Modelling and Inductive Fault Analysis; Functional Yield Modelling; Critical Area and Fault Probability Prediction; Statistical Methods of Parametric Yield and Quality Enhancement; Architectural Fault Tolerance; Design for Test and Manufacturability; Testing Solutions for MCM Manufacturing. (Part contents).