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Performance Optimization in Network-on-Chip (NoC) Architecture
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Artikel-Nr:
9783659523359
Veröffentl:
2014
Einband:
Paperback
Erscheinungsdatum:
23.02.2014
Seiten:
88
Autor:
Nurbaizura Ramji
Gewicht:
149 g
Format:
220x150x6 mm
Sprache:
Englisch
Beschreibung:
Nurbaizura Bt Ramji is a bachelor in Electronic Engineering (Telecommunications) from Universiti Malaysia Sarawak (UNIMAS). Asrani Lit is Research Scientist at UNIMAS.
The escalating complexity of System-on-Chips (SoCs) has resulted bottleneck network communications within the chips thus diminishing its performance. Networks-on-Chip (NoC) was proposed as a paradigm to solve these complications in network communications. As for NoC, the issue arises in designing the topological structure of the on-chip network which fulfilled the application requirements. Therefore, Network Partitioning technique is proposed to obtain the optimal design of networks based on its performance. The performance of NoC is measured through several metrics namely average queue size, waiting time and packet loss. To validate the efficiency, this technique is applied in a case study of MPEG-4 video application. It is expected that the proposed technique is an optimistic way in enhancing the performance of NoC compared to other well known techniques.