Network Partitioning & IP Placement in Network-on-Chip (NoC)

Asrani Hj Lit is with Department of Electronics, Faculty of Engineering, Universiti Malaysia Sarawak (UNIMAS). He obtained his master degree of engineering in Electrical - Microelectronics & Computer System in 2011.He specializes in Network-on-Chip (NoC) communication system modeling.

Among the hardest problem in Networks-on-Chip (NoC) design is to customize the topological structure of the on-chip network in order to fulfill application demand on minimal possible cost. The area cost of NoC is cut down by using Network Partitioning methods where it splits the large network into smaller division. The enhancement in area cost is reached by trimming both router area and the number of global links. From the performance context, Multi-Level Network Partitioning offers a better solution by implemented the concept of clustering. This can be done by putting those heavily communicated cores into the same portion. Therefore, the average internode distances could be minimized. This directly imply a better performance due its to shortest path. For evaluation purpose, some performance metrics are employed which are throughputs, average queue size, probability of packet lost and waiting time. As validation, the proposed technique is experimented with various real System-on-Chip (SoC) applications as case studies.