The Read-Out Controller ASIC for the ATLAS Experiment at LHC

Stefan Popa was born on the 29th of October 1992 in Brasov, Romania. At high-school he focussed on computer science, mathematics and physics, winning awards in county and national level contests and olympiads in computer science and physics.

His association with CERN began in the summer of 2014 when he worked as an undergraduate student for the ATLAS Experiment in networking. In 2015 he continued his studies at Transilvania University of Brasov, graduating with a Master's degree in Integrated Electronics and Communication Systems. In 2017 he started his Ph.D. in the Electronics Engineering, Telecommunications and Information Technology at the same university. He became an ATLAS author in November 2018 (i.e. official recognition of contributions to the Experiment). Since January 2021 he has been employed as a research assistant at Transilvania University of Brasov in parallel to the ATLAS Experiment national project. His PhD thesis was among the six outstanding dissertations receiving the ATLAS thesis prize for 2021.

This thesis presents the complete chain from specifications to real-life deployment of the Read Out Controller (ROC) ASIC for the ATLAS Experiment at LHC, including the design of the FPGA-based setup used for prototype validation and mass testing of the approximately 6000 chips. Long-lasting experiments like the ATLAS at the LHC undergo regular upgrades to improve their performance over time. One of such upgrades of the ATLAS was the replacement of a fraction of muon detectors in the forward rapidities to provide much-improved reconstruction precision and discrimination from background protons. This new instrumentation (New Small Wheel) is equipped with custom-designed, radiation-hard, on-detector electronics with the Read Out Controller chip being a mission-critical element. The chip acts as a clock and control signals distributor and a concentrator, buffer, filter and real-time processor of detector data packets. The described and deployed FPGA-based test setup emulates the asynchronous chip context and employs optimizations and automatic clock and data synchronization. The chip's tolerance to nuclear radiation was evaluated by recording its operation while controlled ultrafast neutron beams were incident to its silicon die. Predictions for the operating environment are made. A proposed implementation of an FPGA Integrated Logic Analyzer that mitigates the observed limitations and constraints of the existing ones is included.