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Die-stacking Architecture
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Artikel-Nr:
9781627057660
Veröffentl:
2015
Seiten:
127
Autor:
Yuan Xie
Serie:
Synthesis Lectures on Computer Architecture
eBook Typ:
PDF
Kopierschutz:
Adobe DRM [Hard-DRM]
Sprache:
Englisch
Beschreibung:
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "e;memory wall"e; problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.
Table of Contents: Preface / Acknowledgments / 3D Integration Technology / Benefits of 3D Integration / Fine-granularity 3D Processor Design / Coarse-granularity 3D Processor Design / 3D GPU Architecture / 3D Network-on-Chip / Thermal Analysis and Thermal-aware Design / Cost Analysis for 3D ICs / Conclusion / Bibliography