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High Performance Multi-Channel High-Speed I/O Circuits
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Artikel-Nr:
9781461449621
Veröffentl:
2013
Einband:
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Erscheinungsdatum:
07.09.2013
Seiten:
100
Autor:
Ramesh Harjani
Gewicht:
325 g
Format:
241x160x11 mm
Serie:
Analog Circuits and Signal Processing
Sprache:
Englisch
Beschreibung:
This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures.
This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. It examines the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s.
Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits
Introduction.- 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process.- 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process.- Adaptive XTCR, AGC, and Adaptive DFE Loop.- Research Summary & Contributions.- References.- Appendix A: Noise Analysis.- Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os ( 4).- Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter.- Appendix D: Line Mismatch Sensitivity.- Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench.- Appendix F: Bandwidth Improvement by Technology Scaling.