VLSI for Artificial Intelligence

This book is an edited selection of the papers presented at the International Workshop on VLSI for Artiflcial Intelligence which was held at the University of Oxford in July 1988. Our thanks go to all the contributors and especially to the programme committee for all their hard work. Thanks are also due to the ACM-SIGARCH, the Alvey Directorate, the lEE and the IEEE Computer Society for publicising the event and to Oxford University for their active support. We are particularly grateful to David Cawley and Paula Appleby for coping with the administrative problems. Jose Delgado-Frias Will Moore October 1988 Programme Committee Igor Aleksander, Imperial College (UK) Yves Bekkers, IRISA/INRIA (France) Michael Brady, University of Oxford (UK) Jose Delgado-Frias, University of Oxford (UK) Steven Krueger, Texas Instruments Inc. (USA) Simon Lavington, University of Essex (UK) Will Moore, University of Oxford (UK) Philip Treleaven, University College London (UK) Benjamin Wah, University of Illinois (USA) Prologue Research on architectures dedicated to artificial intelligence (AI) processing has been increasing in recent years, since conventional data- or numerically-oriented architec tures are not able to provide the computational power and/or functionality required. For the time being these architectures have to be implemented in VLSI technology with its inherent constraints on speed, connectivity, fabrication yield and power. This in turn impacts on the effectiveness of the computer architecture.

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1 Prolog Machines.- 1.1 From Low Level Semantic Description of Prolog to Instruction Set and VLSI Design.- 1.2 A 32 Bit Processor for Compiled Prolog.- 1.3 CARMEL-1: A VLSI Architecture for Flat Concurrent Prolog.- 1.4 VLSI for Parallel Execution of Prolog.- 2 Functional Programming Oriented Architectures.- 2.1 Supporting Functional and Logic Programming Languages through a Data Parallel VLSI Architecture.- 2.2 Translating Declaratively Specified Knowledge and Usage Requirements into a Reconfigurable Machine.- 3 Garbage Collection.- 3.1 VLSI-Appropriate Garbage Collection Support.- 3.2 A Self-timed Circuit for a Prolog Machine.- 4 Content-Addressable Memory.- 4.1 VLSI and Rule-Based Systems.- 4.2 Unify with Active Memory.- 4.3 The Pattern Addressable Memory: Hardware for Associative Processing.- 5 Knowledge Based Systems.- 5.1 A High Performance Relational Algebraic Processor for Large Knowledge Bases.- 5.2 A WSI Semantic Network Architecture.- 6 Neural Architectures.- 6.1 A VLSI Implementation of Multilayered Neural Networks.- 6.2 A Fully Digital Integrated CMOS Hopfield Network Including the Learning Algorithm.- 6.3 A Neural Network for 3-D VLSI Accelerator.- 6.4 Shift Invariant Associative Memory.- 7 Digital and Analog VLSI Neural Networks.- 7.1 VLSI Bit-Serial Neural Networks.- 7.2 A New CMOS Architecture for Neural Networks.- 7.3 A Limited-Interconnect, Highly Layered Synthetic Neural Architecture.- 7.4 VLSI-Design of Associative Networks.- 7.5 Fully-Programmable Analogue VLSI Devices for the Implementation of Neural Networks.- 8 Architectures for Neural Computing.- 8.1 Are Special Chips Necessary for Neural Computing?.- 8.2 A VLSI Systolic Array Dedicated to Hopfield Neural Network.- 8.3 An Integrated System for Neural Network Simulations.