Nanoscaled Semiconductor-on-Insulator Structures and Devices

This proceedings volume constitutes an archive of the contributions of the key-speakers who attended the NATO Advanced Research Workshop on “Nanoscaled Semiconductor-On-Insulator Structures and devices” held in the Tourist and Recreation Centre “Sudak” (Crimea, Ukraine) from 15 to 19 October 2006. The semiconductor industry has sustained a very rapid growth during the last three decades through impressive technological developments which have resulted in products with higher performance and lower cost per function. After many years of development it is now confidently predicted that semiconductor-on-insulator materials will enter and increasingly be used by manufacturing industry. The wider use of semiconductor (es- cially silicon) on insulator materials will not only enable the benefits of these materials to be demonstrated but, also, will drive down the cost of substrates which, in turn, will stimulate the development of other novel devices and applications. Thus the semiconductor-on-insulator materials of today are not only the basis for modern microelectronics but also for future nanoscale devices and ICs. In itself this trend will encourage the promotion of the skills and ideas generated by researchers in the Former Soviet Union and Eastern Europe. Indeed, one of the goals of this Workshop is to promote the development of SOI technologies worldwide.

Proceedings of the NATO Advanced Research Workshop on Nanoscaled Semiconductor-on-Insulator Structures and Devices, Big Yalta, Ukraine, 15-19 October 2006

This book offers combined views on silicon-on-insulator (SOI) nanoscaled electronics from experts in the fields of materials science, device physics, electrical characterization and computer simulation. Coverage analyzes prospects of SOI nanoelectronics beyond Moore’s law and explains fundamental limits for CMOS, SOICMOS and single electron technologies.

Introduction.Nanoscaled SOI Material and Device Technologies.Status and Trends in SOI nanodevices; F. Balestra.- Non-planar devices for nanoscale CMOS; M.C. Lemme et al.- High-k dielectric stacks for nanoscaled SOI devices; S. Hall et al.- Nanoscaled semiconductor heterostructures for CMOS transistors formed by ion implantation and hydrogen transfer; V. Popov et al.- Fluorine – Vacancy Engineering: A viable solution for dopant diffusion suppression in SOI substrates; H.A.W. El Mubarek, P. Ashburn.- Suspended Silicon-On-Insulator nanowires for the fabrication of quadruple gate MOSFETs; V. Passi et al.Physics of Novel Nanoscaled SemOI Devices.Integration of silicon Single-Electron Transistors operating at room temperature; T. Hiramoto.- SiGe nanodots in electro-optical SOI devices; A.V. Dvurechenskii et al.- Nanowire quantum effects in trigate SOI MOSFETs; J.-P. Colinge.- Semiconductor nanostructures and devices; J. Knoch, H. Lüth.- MugFET CMOS process with midgap gate material; W. Xiong et al.- Doping fluctuation effects in multiple-gate SOI MOSFETs; C.A. Colinge et al.- SiGeC HBTs: impact of C on device performance; I.Z. Mitrovic et al.Reliability and Characterization of Nanoscaled SOI Devices.Noise research of nanoscaled SOI devices; N. Lukyanchikova.- Electrical characterization and special properties of FINFET structures; T. Rudenko et al.- Substrate effect on the output conductance frequency response of SOI MOSFETs; V. Kilchytska et al.- Investigation of compressive strain effects induced by STI and ESL; S. Zaouia et al.- Charge trapping phenomena in single electron NVM SOI devices fabricated by a self-aligned quantum dot technology; A. Nazarov et al.Theory and Modeling of Nanoscaled Devices.Variability in nanoscale UTB SOI devices and its impact on circuits and systems; A. Asenov, K. Samsudin.- Electron transport in Silicon-On-Insulator nanodevices; F. Gamiz et al.- All quantum simulation of ultrathin SOIMOSFETs; A. Orlikovsky et al.- Resonant tunneling devices on SOI basis; B. Majkusiak.- Mobility modeling in SOI FETs for different substrate orientations and strain conditions; V. Sverdlov et al.- Three-dimensional (3-D) analytical modeling of the threshold voltage, DIBL and subthreshold swing of cylindrical GATE All Around MOSFETs; H.A. El Hamid et al.Authors Index.