Modeling Microprocessor Performance

Modeling Microprocessor Performance focuses on the development of a design and evaluation tool, named RIPE (Rensselaer Interconnect Performance Estimator). This tool analyzes the impact on wireability, clock frequency, power dissipation, and the reliability of single chip CMOS microprocessors as a function of interconnect, device, circuit, design and architectural parameters. It can accurately predict the overall performance of existing microprocessor systems. For the three major microprocessor architectures, DEC, PowerPC and Intel, the results have shown agreement within 10% on key parameters.
The models cover a broad range of issues that relate to the implementation and performance of single chip CMOS microprocessors. The book contains a detailed discussion of the various models and the underlying assumptions based on actual design practices. As such, RIPE and its models provide an insightful tool into single chip microprocessor design and its performance aspects. At the same time, it provides design and process engineers with the capability to model, evaluate, compare and optimize single chip microprocessor systems using advanced technology and design techniques at an early design stage without costly and time consuming implementation.
RIPE and its models demonstrate the factors which must be considered when estimating tradeoffs in device and interconnect technology and architecture design on microprocessor performance.

1. Introduction.- 1.1. Early CPU Performance Estimators.- 1.2. Current Ongoing Work.- 1.3. RIPE: Rensselaer Interconnect Performance Estimator.- 1.4. National Technology Roadmap For Semiconductors.- 1.5. Summary.- References.- 2. System Level Representation.- 2.1. System Performance Metrics.- 2.2. Microprocessor System Organization.- 2.3. Summary.- References.- 3. Interconnect Parameters.- 3.1. Interconnect Resistance.- 3.2. Interconnect Capacitance.- 3.3. Inductance.- 3.4. Electromigration.- 3.5. Yield.- 3.6. Summary.- References.- 4. Transistor Count and Area Models.- 4.1. Memory Structures.- 4.2. I/O Structures.- 4.3. CPU Logic.- 4.4. Summary.- References.- 5. System Wireability.- 5.1. Wireability Issue.- 5.2. Wiring Methodology.- 5.3. Wiring Distribution Model.- 5.4. Wiring Capacity.- 5.5. Wiring Demand.- 5.6. Total Wiring Demand.- 5.7. Summary.- References.- 6. Device Parameters.- 6.1. Transistor Output Resistance.- 6.2. Effective Logic Gate Output Resistance.- 6.3. Device Capacitance.- 6.4. Logic Gate Capacitance.- 6.5. Summary.- References.- 7. Cycle Time Estimation Model.- 7.1. Critical Path.- 7.2. Propagation Delay Model.- 7.3. Crosstalk.- 7.4. Summary.- References.- 8. System Power Dissipation.- 8.1. Power Dissipation Sources.- 8.2. Power Estimation Methods.- 8.3. Power Estimation.- 8.4. Off-Chip Driver Power Dissipation.- 8.5. Random Logic Power Dissipation.- 8.6. Clock Distribution Power Dissipation.- 8.7. Interconnect Power Dissipation.- 8.8. Memory Power Dissipation.- 8.9. Switching Activity and Activity Factors.- 8.10. Summary.- References.- 9. Microprocessor Performance Evaluation.- 9.1. RIPE Model Benchmarking.- 9.2. 1994 NTRS Performance Predictions.- 9.3. 1994 NTRS Power Dissipation Predictions.- 9.4. 1994 Roadmap and Technology Status.- 9.5. Wiring Capacity and Die Size.- 9.6. Future Work Directions.- 9.7. Book Summary.- References.