Transient-Induced Latchup in CMOS Integrated Circuits

The book all semiconductor device engineers must read to gain a practical feel for latchup-induced failure to produce lower-cost and higher-density chips. Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process. Presents real cases and solutions that occur in commercial CMOS IC chips Equips engineers with the skills to conserve chip layout area and decrease time-to-market Written by experts with real-world experience in circuit design and failure analysis Distilled from numerous courses taught by the authors in IC design houses worldwide The only book to introduce TLU under system-level ESD and EFT tests This book is essential for practicing engineers involved in IC design, IC design management, system and application design, reliability, and failure analysis. Undergraduate and postgraduate students, specializing in CMOS circuit design and layout, will find this book to be a valuable introduction to real-world industry problems and a key reference during the course of their careers.

The book all semiconductor device engineers must read to gain apractical feel for latchup-induced failure to produce lower-costand higher-density chips.Transient-Induced Latchup in CMOS IntegratedCircuits equips the practicing engineer with all thetools needed to address this regularly occurring problem whilebecoming more proficient at IC layout. Ker and Hsu introduce thephenomenon and basic physical mechanism of latchup, explaining thecritical issues that have resurfaced for CMOS technologies. Oncereaders can gain an understanding of the standard practices forTLU, Ker and Hsu discuss the physical mechanism of TLU under asystem-level ESD test, while introducing an efficientcomponent-level TLU measurement setup. The authors then presentexperimental methodologies to extract safe and area-efficientcompact layout rules for latchup prevention, including layout rulesfor I/O cells, internal circuits, and between I/O and internalcircuits. The book concludes with an appendix giving a practicalexample of extracting layout rules and guidelines for latchupprevention in a 0.18-micrometer 1.8V/3.3V silicided CMOSprocess.* Presents real cases and solutions that occur in commercial CMOSIC chips* Equips engineers with the skills to conserve chip layout areaand decrease time-to-market* Written by experts with real-world experience in circuit designand failure analysis* Distilled from numerous courses taught by the authors in ICdesign houses worldwide* The only book to introduce TLU under system-level ESD and EFTtestsThis book is essential for practicing engineers involved in ICdesign, IC design management, system and application designreliability, and failure analysis. Undergraduate and postgraduatestudents, specializing in CMOS circuit design and layout, will findthis book to be a valuable introduction to real-world industryproblems and a key reference during the course of theircareers.

Preface.1 Introduction.1.1 Latchup Overview.1.2 Background of TLU.1.3 Categories of TLU-Triggering Modes.1.4 TLU Standard Practice.References.2 Physical Mechanism of TLU under the System-Level ESDTest.2.1 Background.2.2 TLU in the System-Level ESD Test.2.3 Test Structure.2.4 Measurement Setup.2.5 Device Simulation.2.6 TLU Measurement.2.7 Discussion.2.8 Conclusion.References.3 Component-Level Measurement for TLU under System-Level ESDConsiderations.3.1 Background.3.2 Component-Level TLU Measurement Setup.3.3 Influence of the Current-Blocking Diode and Current-LimitingResistance on the Bipolar Trigger Waveforms.3.4 Influence of the Current-Blocking Diode and Current-LimitingResistance on the TLU Level.3.5 Verifications of Device Simulation.3.6 Suggested Component-Level TLU Measurement Setup.3.7 TLU Verification on Real Circuits.3.8 Evaluation on Board-Level Noise Filters to Suppress TLU.3.9 Conclusion.References.4 TLU Dependency on Power-Pin Damping Frequency and DampingFactor in CMOS Integrated Circuits.4.1 Examples of Different DFreq and DFactor in the System-LevelESD Test.4.2 TLU Dependency on DFreq and DFactor.4.3 Experimental Verification on TLU.4.4 Suggested Guidelines for TLU Prevention.4.5 Conclusion.References.5 TLU in CMOS ICs in the Electrical Fast TransientTest.5.1 Electrical Fast Transient Test.5.2 Test Structure.5.3 Experimental Measurements.5.4 Evaluation on Board-Level Noise Filters to Suppress TLU inthe EFT Test.5.5. Conclusion.References.6 Methodology on Extracting Compact Layout Rules for LatchupPrevention.6.1 Introduction.6.2 Latchup Test.6.3 Extraction of Layout Rules for I/O Cells.6.4 Extraction of Layout Rules for Internal Circuits.6.5 Extraction of Layout Rules between I/O Cells and InternalCircuits.6.6 Conclusion.References.7 Special Layout Issues for Latchup Prevention.7.1 Latchup Between Two Different Power Domains.7.2 Latchup in Internal Circuits Adjacent to Power-Rail ESDClamp Circuits.7.3 Unexpected Trigger Point to Initiate Latchup in InternalCircuits.7.4 Other Unexpected Latchup Paths in CMOS ICs.7.5 Conclusion.References.8 TLU Prevention in Power-Rail ESD Clamp Circuits.8.1 In LV CMOS ICs.8.2 In HV CMOS ICs.8.3 Conclusion.References.9 Summary.9.1 TLU in CMOS ICs.9.2 Extraction of Compact and Safe Layout Rules for LatchupPrevention.Appendix A: Practical Application?Extractions of LatchupDesign Rules in a 0.18-mm 1.8 V/3.3V Silicided CMOSProcess.A.1 For I/O Cells.A.2 For Internal Circuits.A.3 For Between I/O and Internal Circuits.A.4 For Circuits across Two Different Power Domains.A.5 Suggested Layout Guidelines.Index.