Computer Organization and Design

Dr. David Patterson ist Professor für Computer Science an der University of California, Berkeley. Anfang der 1980er Jahren leitetet er zusammen mit Carlo H. Sequin das Berkeley RISC-Projekt das zu RISC I, dem ersten VLSI Reduced Instruction Set Computer führte. Auf dieser Basis entwickelte Sun Microsystems später den SPARC-Prozessor.
Mitte der 1980er Jahre entwickelte Patterson, zusammen mit Randy Katz, das RAID-Konzept (redundant array of independent disks). 1989 arbeitete er am Supercomputer CM-5. Patterson und seine Kollegen versuchten später, einen Supercomputer aus Standard-Desktopcomputern und Switches aufzubauen. Das daraus entstandene NOW-Projekt (Network of Workstations) führte zur Cluster-Technologie. Heute arbeitet er am ROC-Projekt (Recovery Oriented Computing). 2004 bis 2006 war er Präsident der ACM (Association for Computing Machinery).
Patterson ist Autor von über 150 Artikeln und zahlreicher (Lehr-)Bücher; er erhielt rund 30 Auszeichnungen und Ehrungen für seine Tätigkeit in Forschung und Lehre.

Computer Organization and Design, Fourth Edition, provides a new focus on the revolutionary change taking place in industry today: the switch from uniprocessor to multicore microprocessors. This new emphasis on parallelism is supported by updates reflecting the newest technologies with examples highlighting the latest processor designs, benchmarking standards, languages and tools. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Along with its increased coverage of parallelism, this new edition offers new content on Flash memory and virtual machines as well as a new and important appendix written by industry experts covering the emergence and importance of the modern GPU (graphics processing unit), the highly parallel, highly multithreaded multiprocessor optimized for visual computing. This book contains a new exercise paradigm that allows instructors to reconfigure the 600 exercises included in the book to generate new exercises and solutions of their own. The companion CD provides a toolkit of simulators and compilers along with tutorials for using them as well as advanced content for further study and a search utility for finding content on the CD and in the printed text. This text is designed for professional digital system designers, programmers, application developers, and system software developers as well as undergraduate students in Computer Science, Computer Engineering and Electrical Engineering courses in Computer Organization, Computer Design.A new exercise paradigm allows instructors to reconfigure the 600 exercises included in the book to easily generate new exercises and solutions of their own. The companion CD provides a toolkit of simulators and compilers along with tutorials for using them, as well as advanced content for further study and a search utility for finding content on the CD and in the printed text. For the convenience of readers who have purchased an ebook edition or who may have misplaced the CD-ROM, all CD content is available as a download at bit.ly/12XinUx.

Computer Organization and Design, Fourth Edition, provides a new focus on the revolutionary change taking place in industry today: the switch from uniprocessor to multicore microprocessors. This new emphasis on parallelism is supported by updates reflecting the newest technologies with examples highlighting the latest processor designs, benchmarking standards, languages and tools. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Along with its increased coverage of parallelism, this new edition offers new content on Flash memory and virtual machines as well as a new and important appendix written by industry experts covering the emergence and importance of the modern GPU (graphics processing unit), the highly parallel, highly multithreaded multiprocessor optimized for visual computing. This book contains a new exercise paradigm that allows instructors to reconfigure the 600 exercises included in the book to generate new exercises and solutions of their own. The companion CD provides a toolkit of simulators and compilers along with tutorials for using them as well as advanced content for further study and a search utility for finding content on the CD and in the printed text. This text is designed for professional digital system designers, programmers, application developers, and system software developers as well as undergraduate students in Computer Science, Computer Engineering and Electrical Engineering courses in Computer Organization, Computer Design.A new exercise paradigm allows instructors to reconfigure the 600 exercises included in the book to easily generate new exercises and solutions of their own. The companion CD provides a toolkit of simulators and compilers along with tutorials for using them, as well as advanced content for further study and a search utility for finding content on the CD and in the printed text. For the convenience of readers who have purchased an ebook edition or who may have misplaced the CD-ROM, all CD content is available as a download at bit.ly/12XinUx.

1;Front Cover;12;Computer Organization and Design;63;Copyright Page;74;Table of Contents;105;Preface;166;Chapter 1. Computer Abstractions and Technology;276.1;1.1 Introduction;286.2;1.2 Below Your Program;356.3;1.3 Under the Covers;386.4;1.4 Performance;516.5;1.5 The Power Wall;646.6;1.6 The Sea Change: The Switch from Uniprocessors to Multiprocessors;666.7;1.7 Real Stuff: Manufacturing and Benchmarking the AMD Opteron X4;696.8;1.8 Fallacies and Pitfalls;766.9;1.9 Concluding Remarks;796.10;1.10 Historical Perspective and Further Reading;806.11;1.11 Exercises;817;Chapter 2. Instructions: Language of the Computer;997.1;2.1 Introduction;1017.2;2.2 Operations of the Computer Hardware;1027.3;2.3 Operands of the Computer Hardware;1057.4;2.4 Signed and Unsigned Numbers;1127.5;2.5 Representing Instructions in the Computer;1197.6;2.6 Logical Operations;1277.7;2.7 Instructions for Making Decisions;1307.8;2.8 Supporting Procedures in Computer Hardware;1377.9;2.9 Communicating with People;1477.10;2.10 MIPS Addressing for 32-Bit Immediates and Addresses;1537.11;2.11 Parallelism and Instructions: Synchronization;1627.12;2.12 Translating and Starting a Program;1647.13;2.13 A C Sort Example to Put It All Together;1747.14;2.14 Arrays versus Pointers;1827.15;2.15 Advanced Material: Compiling C and Interpreting Java;1867.16;2.16 Real Stuff: ARM Instructions;1867.17;2.17 Real Stuff: x86 Instructions;1907.18;2.18 Fallacies and Pitfalls;1997.19;2.19 Concluding Remarks;2017.20;2.20 Historical Perspective and Further Reading;2047.21;2.21 Exercises;2048;Chapter 3. Arithmetic for Computers;2478.1;3.1 Introduction;2498.2;3.2 Addition and Subtraction;2498.3;3.3 Multiplication;2558.4;3.4 Division;2618.5;3.5 Floating Point;2678.6;3.6 Parallelism and Computer Arithmetic: Associativity;2958.7;3.7 Real Stuff: Floating Point in the x86;2978.8;3.8 Fallacies and Pitfalls;3008.9;3.9 Concluding Remarks;3058.10;3.10 Historical Perspective and Further Reading;3088.11;3.11 Exercises;3089;Chapter 4. The Processor;3239.1;4.1 Introduction;3259.2;4.2 Logic Design Conventions;3289.3;4.3 Building a Datapath;3329.4;4.4 A Simple Implementation Scheme;3419.5;4.5 An Overview of Pipelining;3559.6;4.6 Pipelined Datapath and Control;3699.7;4.7 Data Hazards: Forwarding versus Stalling;3889.8;4.8 Control Hazards;4009.9;4.9 Exceptions;4099.10;4.10 Parallelism and Advanced Instruction-Level Parallelism;4169.11;4.11 Real Stuff: the AMD Opteron X4 (Barcelona) Pipeline;4299.12;4.12 Advanced Topic: an Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations;4319.13;4.13 Fallacies and Pitfalls;4329.14;4.14 Concluding Remarks;4339.15;4.15 Historical Perspective and Further Reading;4349.16;4.16 Exercises;43410;Chapter 5. Large and Fast: Exploiting Memory Hierarchy;47510.1;5.1 Introduction;47710.2;5.2 The Basics of Caches;48210.3;5.3 Measuring and Improving Cache Performance;50010.4;5.4 Virtual Memory;51710.5;5.5 A Common Framework for Memory Hierarchies;54310.6;5.6 Virtual Machines;55010.7;5.7 Using a Finite-State Machine to Control a Simple Cache;55410.8;5.8 Parallelism and Memory Hierarchies: Cache Coherence;55910.9;5.9 Advanced Material: Implementing Cache Controllers;56310.10;5.10 Real Stuff: the AMD Opteron X4 (Barcelona) and Intel Nehalem Memory Hierarchies;56410.11;5.11 Fallacies and Pitfalls;56810.12;5.12 Concluding Remarks;57210.13;5.13 Historical Perspective and Further Reading;57310.14;5.14 Exercises;57311;Chapter 6. Storage and Other I/O Topics;59311.1;6.1 Introduction;59511.2;6.2 Dependability, Reliability, and Availability;59811.3;6.3 Disk Storage;60011.4;6.4 Flash Storage;60511.5;6.5 Connecting Processors, Memory, and I/O Devices;60711.6;6.6 Interfacing I/O Devices to the Processor, Memory, and Operating System;61111.7;6.7 I/O Performance Measures: Examples from Disk and File Systems;62111.8;6.8 Designing an I/O S