Three-Dimensional Integrated Circuit Design

He is currently an Assistant Professor in the School of Computer Science at the University of Manchester, Manchester, UK. From 2008 to 2012, he was a post-doctoral fellow with the Integrated Systems Laboratory at the Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland. He was with INTRACOM S.A., Athens, Greece, from 2000 to 2002. He has also been a visiting researcher at Synopsys Inc., Mountain View, CA, with the Primetime group in 2007. His current research interests include interconnect modeling and analysis, 3-D and 2.5-D integration, and other issues related to VLSI design. He has published several conference and journal papers in these areas. He was the leading designer of the Rochester cube and co-creator of the Manchester Thermal Analyzer.

Dr. Pavlidis is on the editorial board of the Microelectronics Journal and Integration, the VLSI Journal. He also serves on the Technical Program Committees of several IEEE conferences. He is a member of the VLSI Systems & Applications Technical Committee of the Circuits and Systems Society and a member of the IEEE. He is also involved in public policy issues as a member of the ICT working group of the IEEE European Public Policy Initiative.

He is currently an Assistant Professor with the Department of Electrical and Computer Engineering at Drexel University, Philadelphia, PA, USA, where he directs the Integrated Circuits and Electronics (ICE) Design and Analysis Laboratory. He has held visiting research positions with the 3-D Integration group at Freescale Semiconductor, Austin, TX, USA in 2007, and the System on Package and 3-D Integration group at the IBM T. J. Watson Research Center, Yorktown Heights, NY, in 2008, 2009, 2010, and 2011. His current research and teaching interests include analysis, modeling, and design methodologies for high performance digital and mixed-signal integrated circuits, power management for SoC and microprocessor circuits (including on-chip dc-dc converters), emerging integrated circuit technologies, IC design for trust (hardware security), and interconnect related issues in 2-D and 3-D ICs. He has authored or co-authored over 40 technical papers published in peer-reviewed journals and conferences, and holds 4 pending patents.

Dr. Savidis is a member of the editorial boards of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, the Microelectronics Journal, and the Journal of Circuits, Systems and Computers. He serves on the Organizing Committees and Technical Program Committees of many international conferences including the IEEE International Symposium on Circuits and Systems, the Great Lakes Symposium on Very Large Scale Integration, the ACM/IEEE System Level Interconnect Prediction Workshop, and the IEEE International Symposium on Hardware Oriented Security and Trust.

Eby G. Friedman received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering.

From 1979 to 1991, he was with Hughes Aircraft Company, rising to the position of manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance digital and analog integrated circuits. He has been with the Department of Electrical and Computer Engineering at the University of Rochester since 1991, where he is a Distinguished Professor, and the Director of the High Performance VLSI/IC Design and Analysis Laboratory. He is also a Visiting Professor at the Technion - Israel Institute of Technology. His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors, low power wireless communications, and power efficient server farms.

He is the author of more than 500 papers and book chapters, 13 patents, and the author or editor of 18 books in the fields of high speed and low power CMOS design techniques, 3-D integration, high speed interconnect, and the theory and application of synchronous clock and power delivery and management. Dr. Friedman is the Editor-in-Chief of the Microelectronics Journal, a Member of the editorial board of the Journal of Low Power Electronics and Journal of Low Power Electronics and Applications, and a Member of the technical program committee of numerous conferences. He previously was the Editor-in-Chief and Chair of the Steering Committee of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, the Regional Editor of the Journal of Circuits, Systems and Computers, a Member of the editorial board of the Proceedings of the IEEE, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Analog Integrated Circuits and Signal Processing, and Journal of Signal Processing Systems, a Member of the Circuits and Systems (CAS) Society Board of Governors, Program and Technical chair of several IEEE conferences, and a recipient of the IEEE Circuits and Systems 2013 Charles A. Desoer Technical Achievement Award, a University of Rochester Graduate Teaching Award, and a College of Engineering Teaching Excellence Award. Dr. Friedman is an inaugural member of the University of California, Irvine Engineering Hall of Fame, a Senior Fulbright Fellow, and an IEEE Fellow.

Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits.

Expanded with new chapters and updates throughout based on the latest research in 3-D integration:

• Manufacturing techniques for 3-D ICs with TSVs
• Electrical modeling and closed-form expressions of through silicon vias
• Substrate noise coupling in heterogeneous 3-D ICs
• Design of 3-D ICs with inductive links
• Synchronization in 3-D ICs
• Variation effects on 3-D ICs
• Correlation of WID variations for intra-tier buffers and wires

• Offers practical guidance on designing 3-D heterogeneous systems
• Provides power delivery of 3-D ICs
• Demonstrates the use of 3-D ICs within heterogeneous systems that include a variety of materials, devices, processors, GPU-CPU integration, and more
• Provides experimental case studies in power delivery, synchronization, and thermal characterization

1. Introduction 2. Manufacturing of 3-D Packaged Systems 3. 3-D Integrated Circuit Fabrication Technologies 4. Electrical Modeling and Closed-Form Expressions of Through Silicon Vias 5. Substrate Noise Coupling in Heterogeneous 3-D ICs 6. Design of 3-D ICs with Inductive Links 7. Interconnect Prediction Models 8. Cost Issues for 3-D Integrated Systems 9. Physical Design Techniques for 3-D ICs 10. Timing Optimization for Two-Terminal Interconnects 11. Timing Optimization for Multi-Terminal Interconnects 12. Thermal Modeling and Analysis 13. Thermal Management Strategies for 3-D ICs 14. Case Study: Thermal Effects in a prototype 3-D IC 15. Three-Dimensional Networks-on-Chip 16. Synchronization in 3-D ICs 17. Case Study: Clock distribution in 3-D ICs 18. Variation Effects on 3-D ICs 19. Power Delivery and Distribution for 3-D ICs 20. Case Study: Power Distribution Networks in 3-D ICs 21. Conclusions and Future Prospects

Appendix A: Enumeration of Gate Pairs in a 3-D IC B: Formal Proof of Optimum Single Via Placement C: Proof of the Two-Terminal Via Placement Heuristic D: Proof of Condition for Via Placement of Multi-Terminal Nets Glossary E: Correlation of WID Variations for Intra-Tier Buffers F: Extension of the Proposed Model to Include Variations of Wires